Copper wiring for on-chip interconnections, currently fabricated by a (single or dual) Damascene integration approach, is surrounded on the sides and at the bottom by a liner or barrier (e.g.—Ta, W, nitrides thereof and multilayers thereof), whose role is to prevent Cu diffusion into the interlayer dielectric material (ILD) (e.g. SiO2 and low k dielectrics) and to provide excellent adhesion between the Cu conductor and the ILD. Additionally, the liner prevents the diffusion of O2 or other substances into the Cu conductor. The diffusion of such materials would cause chemical changes to the conductor and adversely affect its resistivity and other properties. Recent work by Hu et al., “Electromigration in On-Chip Single/Dual Damascene Cu Interconnections”, J. Electrochem. Soc., 149, G408 (2002); and Hu et al. “Scaling Effect on Electromigration in On-Chip Cu Wiring”, Proc. IITC (1999) p. 267; C.-K. Hu and S. Reynolds, “CVD Cu Interconnections and Electromigration”, Electrochem. Soc. Proc. Vol. 97–25 (1997), p. 1514, has shown that surface diffusion is a predominant way for Cu to electromigrate; it is therefore evident that good adhesion of the Cu conductor to the liner helps suppress electromigration. Materials such as Ta/TaN bilayers have been shown to be excellent diffusion barriers and to provide excellent adhesion and electromigration suppression. For example, see Edelstein, et al. “A High Performance Liner for Copper Damascene Interconnects,” Proceedings of the 2001 IEEE IITC, pp 9–11, (2001).
Providing an appropriate capping material on the copper suppresses electromigration of the copper conductor material. Although Damascene integration provides a facile way to protect Cu conductors on the side and at the bottom, it does not provide a satisfactory solution at the top of the structure.
Capping the top of these structures poses more of a challenge due to the desire for planarity between layers in fabricating a multilayer interconnects structure. Electroless plating has been demonstrated to selectivity deposit on the interconnect; however, this approach offers only a limited set of materials and lacks planarity between layers. Also, presently, to suppress Cu diffusion or electromigration from the top, a blanket film of a material such as SixNy is deposited after the Cu and surrounding ILD is planarized and before the subsequent layer of metallization is built (FIG. 1). Although such layers have proven adequate for past generation of processors, the drive towards reduction of the effective interlayer dielectric constant and increased protection against electromigration suggest that new materials and integration approaches should be developed that are selectively deposited on top of the Cu conductors (FIG. 1). It is apparent that blanket films, even if they address the electromigration and diffusion problems, may cause an unacceptable increase in the overall dielectric constant of the structure.
Accordingly, the present invention relates to improved methods and apparatus for selectively capping copper.